The present invention relates to a power circuit of a PWM inverter for PWM controlling the coil voltage of an electric motor.
PWM is an abbreviation of Pulse Width Modulation and is a technique widely utilized in the field of motor control.
Recently, use of the PWM inverter has spread rapidly and it is now widely utilized to control electric motors. FIG. 19 is a schematic diagram illustrating a three-phase PWM inverter as an example of a general PWM inverter. In the PWM inverter, generally, the number of output circuits 53 is different depending on the number of phases of the electric motor used, while the basic operation thereof is identical.
Referring to FIG. 19, the configuration of the general three-phase PWM inverter will be described.
A basic frequency and an effective voltage value of a three-phase AC voltage waveform supplied to an electric motor 60 are set in frequency and voltage setting means 58. A PWM control circuit 59 generates three-phase PWM signals therein on the basis of the information set in the frequency and voltage setting circuit 58 to output them as switching command signals 42, 61 and 62. The switching command signals 42, 61 and 62 are binary signals for commanding whether winding terminals 52, 63 and 64 of the motor are connected to a positive terminal of a DC main power supply 14 or a negative terminal thereof. The frequency of the switching command signal 42, 61 or 62 is named a PWM carrier frequency and is generally ten times or more as large as the basic frequency of the three-phase AC voltage waveform supplied to the motor 60. Generally, in many cases, the basic frequency of the three-phase AC voltage waveform supplied to the motor is about 0 to 200 Hz and the PWM carrier frequency is about 2 to 20 kHz. A motor release signal 156 is a binary signal for commanding whether the motor is made to operate in a free-running state or not. The free-running state is a state in which all of the winding terminals 52, 63 and 64 of the motor are connected to neither the positive terminal nor the negative terminal of the DC main power supply 14, and when any trouble occurs, the motor is set to this state in order to protect the motor and control devices generally. The output circuit 53 of the PWM inverter is a semiconductor switch circuit for controlling connecting of the winding terminal 52, 63 or 64 to the positive terminal or the negative terminal of the DC main power supply 14 in accordance with the switching command signal 42, 61 or 62. Further, it is configured so that the winding terminal 52, 63 or 64 of the motor is not connected to either the positive terminal or the negative terminal of the DC main power supply 14 in spite of the switching command signal 42, 61 or 62 when the motor release signal 156 commands the free-running state. In general, the voltage of the DC main power supply is often about DC 140 V obtained by rectifying and smoothing AC 100 V or about DC 280 V obtained by rectifying and smoothing AC 200 V.
A conventional output circuit of the PWM inverter is now described.
FIG. 20 schematically illustrates a conventional output circuit of the PWM inverter.
In FIG. 20, numeral 65 denotes logic inversion means for inverting a logic of the switching command signal 42 to output an inverted switching signal 80. Numerals 157 and 158 denote AND means for taking an AND of the motor release signal 156 and the switching command signal 42 to output the AND signal as an upper arm switching signal 159 and for taking an AND of the motor release signal 156 and the inverted switching signal 80 to output the AND signal as a lower arm switching signal 160, respectively. Numerals 66 and 67 denote on-delay circuits for delaying respective rising edges of the upper arm switching signal 159 and the lower arm switching signal 160 by an on-delay time TD to output an upper arm control signal 81 and a lower arm control signal 82, respectively. Numerals 68 and 69 denote base drive circuits for turning on and off a power transistor 70 in response to the upper arm control signal 81 and a power transistor 71 in response to the lower arm control signal 82, respectively. More particularly, when the upper arm control signal 81 becomes "H" level, an output transistor of a photocoupler 72 is turned on to thereby turn on a transistor 74 with the result that a transistor 76 is turned off to thereby turn on the power transistor 70. On the contrary, when the upper arm control signal 81 becomes "L" level, the output transistor of the photocoupler 72 is turned off to thereby turn off the transistor 74 with the result that the transistor 76 is turned on to thereby turn off the power transistor 70.
As the base drive circuit, there are other base drive circuits described in JP-U-57-42589 and JP-A-59-178980. These base drive circuits may function basically in the same manner as the base drive circuits 68 and 69 shown in FIG. 20 and may be employed instead of the circuit shown in FIG. 20.
Operation of the output circuit of the PWM inverter configured above is now described.
First of all, it is assumed that the motor release signal 156 is "L" level, that is, the free-running state is commanded. In this case, it will be understood that the power transistors 70 and 71 are off whether the switching command signal 42 is "L" level or "H" level.
Description is now made to the case where the motor release signal 156 is "H" level, that is, a state that is not the free-running state is commanded.
FIG. 21 shows waveforms of signals in the output circuit of the PWM inverter shown in FIG. 20. When the switching command signal 42 is changed from "L" level to "H" level, the on-delay circuit 66 changes the upper arm control signal 81 from "L" level to "H" level after the delay time TD. When the upper arm control signal 81 becomes "H" level, the power transistor 70 is turned on with a delay time TX1 by the base drive circuit 68 and remains on until after the upper arm control signal 81 has become "L" level. The delay time TX1 varies in accordance with variations in the temperature of the power transistor 70 and the current flowing through the collector thereof, and also varies due to scattering and long term changes of the power transistor and components constituting the base drive circuit.
Further, when the switching command signal 42 changes from "L" level to "H" level, the inverted switching signal 80 is changed from "H" level to "L" level, so that the on-delay circuit 67 changes the lower arm control signal 82 to "L" level substantially immediately. When the lower arm control signal 82 becomes "L" level, the power transistor 71 is turned off with a delay time TY2 by the base drive circuit 69 and remains off until after the lower arm control signal 82 has become level. The delay time TY2 varies in accordance with variations in the temperature of the power transistor 71 and the current flowing through the collector thereof, and also varies due to scattering and long term changes of the power transistor and components constituting the base drive circuit.
When the switching command signal 42 changes from "H" level to "L" level, the on-delay circuit 66 changes the upper arm control signal 81 to "L" level substantially immediately and the power transistor 70 is turned off with a delay time TY1 by the base drive circuit 68 and remains off until after the upper arm control signal 81 has been changed to "H" level.
When the switching command signal 42 is changed from "H" level to "L" level, the inverted switching signal 80 is changed from "L" level to "H" level, so that the on-delay circuit 67 changes the lower arm control signal 82 from "L" level to "H" level after the on-delay time TD. When the lower arm control signal 82 is changed to "H" level, the power transistor 71 is turned on with a delay time TX2 by the base drive circuit 69 and remains on until after the lower arm control signal 82 has been changed to "L" level.
When the delay time TX1 or TX2 is compared with the delay time TY1 or TY2, there is a tendency for the delay time TY1 or TY2 to be longer than the delay time TX1 or TX2 generally. When it is assumed that the shortest value of the delay times TX1 and TX2 is TXW in consideration of the worst condition thereof and the longest value of the delay times TY1 and TY2 is TYW in consideration of the worst condition thereof, the on-delay time TD is usually set to a time equal to the sum of a value obtained by subtracting TXW from TYW and a slight margin. Usually, the on-delay time TD is set to about 10 to 50 micro seconds when a bipolar type power transistor is used, set to about 5 to 30 micro seconds when an IGBT is used, or set to about 2 to 10 micro seconds when a power MOS-FET is used. IGBT is an abbreviation of insulated gate bipolar transistor and used hereinbelow. Thus, the circuit prevents both of the power transistors 70 and 71 from being on simultaneously to thereby produce a short-circuit between the positive terminal and the negative terminal of the DC main power supply 14 when the switching command signal 42 is changed from "H" level to "L" level or from "L" level to "H" level.
From the foregoing, when attention is paid to the states of the switching command signal 42 and the voltage 51 of the motor winding terminal, since the power transistor 70 is off and the power transistor 71 is on when the switching command signal 42 is switched to the "L" level, the motor winding terminal 52 is connected to the negative terminal of the DC main power supply 14 whereas since the power transistor 70 is on and the power transistor 71 is off when the switching command signal 42 is switched to the "H" level, the motor winding terminal 52 is connected to the positive terminal of the DC main power supply 14.
In the above circuit configuration, however, in the case where the motor release signal 156 is "H" level, that is, a state other than the free-running state is commanded, when the switching command signal 42 is changed from "L" level to "H" level and from "H" level to "L" level, both of the power transistors 70 and 71 are off during a certain time and this off state of both the power transistors causes a control error in the case where the motor winding terminal 52 is voltage-controlled. There is a problem that the control error causes variation of torque generated and the rotational speed of the motor, and also increases noise due to vibration of the motor.
This problem is now described in more detail.
In FIGS. 20 and 21, when the switching command signal 42 is changed from "L" level to "H" level and from "H" level to "L", the power transistor being in the on state is first turned off and thereafter the power transistor being in the off state is turned on. Accordingly, the power transistors 70 and 71 are both in the off state during a certain time. This state is named a floating state and this time is named a floating time TZ. Generally, the floating time TZ is often about a half to two thirds of the on-delay time TD.
In general, the PWM control of the motor is essentially made so that the motor winding terminals are alternately connected to the positive terminal and the negative terminal of the DC main power supply to control an average voltage of the motor winding terminal in accordance with the ratio of the time of connection to the positive terminal and then time of connection to the negative terminal. Accordingly, when the voltage of the DC main power supply 14 is fixed, it is ideal that the average voltage of the motor winding terminal 52 can be controlled uniquely in accordance with the ratio of the "H" level and "L" level of the switching command signal 42.
In the conventional output circuit of the PWM inverter, however, the average voltage of the motor winding terminal is varied depending on the direction of the current flowing through the motor winding terminal since the floating state exists. More particularly, when the floating state occurs in the state where a current flows from the motor winding terminal 52 into the output circuit 53 of the PWM inverter, a diode 78 is conductive, so that the motor winding terminal 52 is connected to the positive terminal of the DC main power supply 14. This state is shown by a voltage 51A of the motor winding terminal in FIG. 21. On the contrary, when a current flows from the output circuit 53 of the PWM inverter into the motor winding terminal 52 in the floating state, a diode 79 is conductive, so that the motor winding terminal 52 is connected to the negative terminal of the DC main power supply 14. This state is shown by a voltage 51B of the motor winding terminal in FIG. 21. In the floating state, when no current flows in the motor winding terminal 52, the voltage of the motor winding terminal 52 is determined by an induced voltage generated within the motor 60.
As described above, the switching command signal 42 and the average voltage of the motor winding terminal 52 are not uniquely determined due to the floating state, and accordingly the control error occurs. Usually, since the current flowing through the motor winding terminal 52 is an alternating current and the direction thereof is varied, the control error is also varied correspondingly and the generated torque and the rotational speed of the motor 60 are varied. This problem can be solved by removing the floating state and reducing the floating time to zero, while in the conventional output circuit of the PWM inverter the positive terminal and the negative terminal of the DC main power supply 14 are short-circuited and accordingly it is actually impossible to remove the floating state and reduce the floating time to zero.
Further, electric noise occurs when the power transistors are turned on and off. This noise can be reduced where it is particularly desirable to do so by connecting a condenser between the base and the emitter of each of the power transistors but this often results in a reduction in switching speed. However, the delay times TX1, TX2, TY1 and TY2 are greatly scattered by reducing the switching speed, and the floating time should be further increased. Accordingly, the control error is increased and consequently the switching speed can not be reduced much.
There is a conventional output circuit of the PWM inverter in which the power transistors 70 and 71 of FIG. 19 are replaced by IGBT's and another conventional output circuit of the PWM inverter in which the power transistors 70 and 71 of FIG. 20 are replaced by power MOS-FET's. However, the operation thereof is quite identical with that of the output circuit of the PWM inverter shown in FIG. 20 and the circuits also have the floating state.